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16-bit, 8-channel, 250 ksps pulsar ? adc preliminary technical data AD7689 rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 16-bit resolution with no missing codes 8-channel multiplexer with: unipolar single ended or differential (gnd sense)/bipolar inputs throughput: 250 ksps inl/dnl: 0.6 lsb typical dynamic range: 93.5 db sinad: 92.5 db @ 20 khz thd: ?100 db @ 20 khz analog input range: 0 v to v ref with v ref up to vdd reference: internal selectable 2.5 v/4.096 v or external buffered (up to 4.096 v) external (up to vdd) internal temperature sensor channel sequencer, selectable 1-pole filter, busy indicator no pipeline delay, sar architecture single-supply 2.7v C 5.5 v operation with 1.8 v to 5 v logic interface serial interface spi?/qspi?/microwire?/dsp compatible power dissipation: 6 mw @ 5 v/100 ksps standby current: 1 na 20-lead 4 mm 4 mm lfcsp package applications battery-powered equipment medical instruments mobile communications personal digital assitants data acquisition seismic data acquisition systems instrumentation process control functional block diagram AD7689 ref gnd vdd vio din sck sdo cnv 1.8v to vdd 2.7v to 5v sequencer spi serial interface mux 16-bit sar adc band gap ref temp sensor refin in0 in1 in4 in5 in6 in7 in3 in2 com 0.5v to vdd 22 f 1-pole lpf 0.5v to 4.096v 0.1 f figure 1. table 1. multichannel14-/16-bit pulsar adc type channels 250 ksps 500 ksps adc driver 14-bit 8 ad7949 ada4841-x 16-bit 4 ad7682 ada4841-x 16-bit 8 AD7689 ad7699 ada4841-x general description the AD7689 is an 8-channel 16-bit, charge redistribution successive approximation register (sar), analog-to-digital converter (adc) that operates from a single power supply, vdd. the AD7689 contains all of the components for use in a multi- channel, low power, data acquisition system including: a true 16- bit sar adc with no missing codes; an 8-channel, low crosstalk multiplexer useful for configuring the inputs as single ended (with or without ground sense), differential or bipolar; an internal low drift reference (selectable 2.5v or 4.096v) and buffer; a temperature sensor; a selectable 1-pole filter; and a sequencer useful when channels are continuously scanned in order. the AD7689 uses a simple spi interface for writing to the configuration register and receiving conversion results. the spi interface uses a separate supply, vio, which is set to the host logic level. power dissipation scales with throughput. the AD7689 is housed in a tiny 20-lead lfcsp with operation specified from ?40c to +85c.
AD7689 preliminary technical data rev. prc | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 10 theory of operation ...................................................................... 11 overview...................................................................................... 11 converter operation.................................................................. 11 transfer functions...................................................................... 12 typical connection diagram ................................................... 12 configuration register, cfg .................................................... 13 analog inputs ............................................................................. 13 driver amplifier choice ........................................................... 14 voltage reference output/input .............................................. 15 power supply............................................................................... 16 supplying the adc from the reference.................................. 16 digital interface.......................................................................... 16 without busy indicator ............................................................. 17 with busy indicator................................................................... 18 application hints ........................................................................... 19 layout .......................................................................................... 19 evaluating AD7689 performance............................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history
preliminary technical data AD7689 rev. prc | page 3 of 20 specifications vdd = 2.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit resolution 16 bits analog input voltage range unipolar mode 0 +v ref v bipolar mode ?v ref /2 +v ref /2 absolute input voltage positive input, unipolar and bipolar mode ?0.1 v ref + 0.1 v negative or com input, unipolar mode ?0.1 +0.1 negative or com input, bipolar mode v ref /2 C 0.1 v ref /2 v ref /2 + 0.1 analog input cmrr f in = 250 khz tbd db leakage current at 25c acquisition phase 1 na input impedance 1 throughput conversion rate vdd = 4.096v to 5.5 0 250 ksps vdd = 2.5v to 4.096v 1 200 transient response full-scale step 1.8 s accuracy no missing codes 16 bits integral linearity error -2 0.6 +2 lsb 2 differential linearity error ?1 0.25 +1.5 lsb transition noise ref = vdd = 5 v 0.5 lsb gain error 3 ?30 0.5 +30 lsb gain error match tbd lsb gain error temperature drift 0.3 ppm/c offset error 3 ?5 0.5 +5 lsb offset error match tbd lsb offset error temperature drift 0.3 ppm/c power supply sensitivity vdd = 5 v 5% 1 ppm ac accuracy 4 dynamic range 93.5 db 5 signal-to-noise f in = 20 khz, vref = 5v 92.5 db f in = 20 khz, vref = 2.5v 88.5 signal-to-(noise + distortion) f in = 20 khz, vref = 5v 92.5 db f in = 20 khz, vref = 2.5v 88.5 db total harmonic distortion f in = 20 khz ?100 db spurious-free dynamic range f in = 20 khz 110 db channel-to-channel crosstalk f in = 100 khz on adjacent channel(s) -117 db intermodulation distortion 6 115 db sampling dynamics ?3 db input bandwidth selectable 0.425 1.7 mhz aperture delay vdd = 5v 2.5 ns 1 see the analog inputs section. 2 lsb means least significant bit. with the 5 v input range, one lsb is 76.3 v. 3 see the terminology section. these specif ications include full temperature range variation but not the error contribution from the external reference. 4 with v ref = 5 v, unless otherwise noted. 5 all specifications expressed in decibels are referred to a full-scale input fsr and tested with an input signal at 0.5 db belo w full scale, unless otherwise specified. 6 f in1 = 21.4 khz and f in2 = 18.9 khz, with each tone at ?7 db below full scale.
AD7689 preliminary technical data rev. prc | page 4 of 20 vdd = 2.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 3. parameter conditions/comments min typ max unit internal reference output voltage for 4.096 v output, @ 25c 4.086 4.096 4.106 v for 2.5 v output, @ 25c 2.490 2.500 2.510 v temperature drift C40c to +85c tbd ppm/c line regulation vdd = 5 v 5% tbd ppm/v long-term drift 1000 hours 50 ppm turn-on settling time c ref = 22 f tbd ms external reference voltage range ref input 0.5 vdd + 0.3 v refin input (buffered) 0.5 4.096 v current drain 250 ksps, ref = 5v 50 a temperature sensor output voltage 1 @ 25c 283 mv temperature sensitivity 1 mv/c digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format 2 pipeline delay 3 v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 2.3 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 4, 5 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 5v , 100 ksps throughput 6 mw vdd = 5v , 250 ksps throughput 15 mw vdd = 5v , 250 ksps throughput internal reference and buffer enabled 18.5 mw energy per conversion 50 nj temperature range 6 specified performance t min to t max ?40 +85 c 1 the output voltage is internal and pr esent on a dedicated multiplexer input. 2 unipolar mode: serial 16-bit straight binary bipolar mode: serial 16-bit 2s complement. 3 conversion results available immediately after completed conversion. 4 with all digital inputs forced to vio or gnd as required. 5 during acquisition phase. 6 contact an analog devices sales representative for the extended temperature range.
preliminary technical data AD7689 rev. prc | page 5 of 20 timing specifications vdd = 4.5 v to 5.5 v , vio = 2.3 v to vdd, all specifications t min to t max , unless otherwise noted. table 4. 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 2.2 s acquisition time t acq 1.8 s time between conversions t cyc 4 s cnv pulse width t cnvh 10 ns sck period t sck 15 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 4 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv low to sdo d15 msb valid t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv high or last sck falling edge to sdo high impedance t dis 25 ns cnv high to sck low t csck 10 ns din valid setup time from sck falling edge t sdin 4 ns din valid hold time from sck falling edge t hdin 4 ns 1 see figure 2 and figure 3 for load conditions.
AD7689 preliminary technical data rev. prc | page 6 of 20 vdd = 2.5 v to 4.5 v , vio = 2.3 v to vdd, all specifications t min to t max , unless otherwise noted. table 5. 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.7 3.2 s acquisition time t acq 1.8 s time between conversions t cyc 5 s cnv pulse width t cnvh 10 ns sck period t sck 25 ns sck low time t sckl 12 ns sck high time t sckh 12 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 3 v 24 ns vio above 2.7 v 30 ns vio above 2.3 v 35 ns cnv low to sdo d15 msb valid t en vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv high or last sck falling edge to sdo high impedance t dis 25 ns cnv high to sck low t csck 10 ns sdi valid setup time from sck falling edge t sdin 5 ns sdi valid hold time from sck falling edge t hdin 4 ns 1 see figure 2 and figure 3 for load conditions. 500a i ol 500a i oh 1.4v t o sdo c l 50pf - 00 2 figure 2. load circuit fo r digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 1. 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2. 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. - 003 figure 3. voltage levels for timing
preliminary technical data AD7689 rev. prc | page 7 of 20 absolute maximum ratings table 6. parameter rating analog inputs inn, 1 com 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref, refin gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v din, cnv, sck to gnd ?0.3 v to vio + 0.3 v sdo to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (msop-10) 200c/w jc thermal impedance (msop-10) 44c/w 1 see analog inputs section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD7689 preliminary technical data rev. prc | page 8 of 20 pin configurations and function descriptions pin 1 indicator 1 vdd 2 ref 3 refin 4 gnd 5 gnd 13 sck 14 sdo 15 vio 12 din 11 cnv 6 i n 4 7 i n 5 8 i n 6 1 0 c o m 9 i n 7 1 8 i n 2 1 9 i n 3 2 0 v d d 1 7 i n 1 1 6 i n 0 top view 00000-004 figure 4. 20-lead lfcsp pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1, 20 vdd p power supply. nominally 2.5 v to 5.5 v when usin g an external reference, and decoupled with 10 f and 100 nf capacitors. when using the internal reference for 2. 5v output, the minimum should be 2.7v. when using the internal reference for 4. 096v output, the minimum should be 4.5v. 2 ref ai/o reference input/output. see the voltage reference output/input section. when the internal reference is enabled, this pin produces a selectable system reference = 2.5v or 4.096v. when the internal reference is disabled and th e buffer is enabled, ref produces a buffered version of the voltage present on the refin pin (4.096v max.) useful when using low cost, low power references. for improved drift performance, connect a precision reference to ref (0.5v to vdd). for any reference method, this pin needs deco upling with an external a 22 f capacitor connected as close to ref as possible. see the reference decoupling section. 3 refin ai/o internal reference output/reference buffer input. see the voltage reference output/input section. when using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1f capacitor. when using the internal reference buffer, appl y a source between 0.5v to 4.096v which is buffered to the ref pin as described above. 4, 5 gnd ai power supply ground. 6 - 9 in4 C in7 ai channel 4 through channel 7 analog inputs. 10 com ai common channel input. all channels [7:0] can be referenced to a common mode point of 0 v or v ref /2 v. 11 cnv di convert input. on the rising edge, cnv initiates the conversion. during conversion, if cnv is held high, the busy indictor is enabled. 12 din di data input. this input is used for writing to the 14-bit configuration register. the configuration register can be written to during and after conversion. 13 sck di serial data clock input. this inp ut is used to clock out the data on ado and clock in data on din in an msb first fashion. 14 sdo do serial data output. the conversion result is output on this pin synchronized to sck. in unipolar modes, conversion results are straight binary; in bipolar modes conversion results are twos complement. 15 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 16 - 19 in0 C in3 ai channel 0 through channel 3 analog inputs. 1 ai = analog input, ai/o = analog input/output, di = digital input, do = digital output, and p = power.
preliminary technical data AD7689 rev. prc | page 9 of 20 typical performance characteristics -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 16384 32768 49152 65536 code inl (lsb) figure 5. integral nonlinearity vs. code, vref = 5v 00 44 76 00 36872 27695 196433 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 200000 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 code in hex counts = 0.44 v ref = 5v figure 6. histogram of a dc input at code center, vref = 5v -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 2 5 5 0 7 5 1 0 0 1 2 5 frequency (khz) amplitude (db of full scale) f s = 250 ksps f in = 10.1 khz snr = 91.1 db thd = -102 db sfdr = 103 db sinad = 91 db figure 7. 10khz fft, vref = 5v -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 0 16384 32768 49152 65536 code dnl (lsb) figure 8. differential nonlinearity vs. code, vref = 5v 00 784 50640 171449 37789 457 10 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 200000 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 8002 code in hex counts = 0.83 v ref = 2.5v figure 9. histogram of a dc input at code center, vref = 2.5v -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 2 5 5 0 7 5 1 0 0 1 2 5 frequency (khz) amplitude (db of full scale) f s = 250 ksps f in = 10.1 khz snr = 87.1 db thd = -104 db sfdr = 104 db sinad = 87 db figure 10. 10khz fft, vref = 2.5v
AD7689 preliminary technical data rev. prc | page 10 of 20 terminology least significant bit (lsb) the lsb is the smallest increment that can be represented by a converter. for an analog-to-digital converter with n bits of resolution, the lsb expressed in volts is n ref v lsb 2 (v) = integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 12). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.14 v). the unipolar offset error is the deviation of the actual transition from that point. gain error the last transition (from 11110 to 11111) should occur for an analog voltage 1? lsb below the nominal full-scale. the gain error is the deviation in lsb (or % of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. closely related is the full-scale error (also in lsb or % of full-scale range), which includes the effects of the offset error. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accurately acquire its input after a full-scale step function is applied. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. channel-to-channel crosstalk channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. it is measured by applying a dc to the channel under test and applying a full-scale, 100 khz sine wave signal to the adjacent channel(s). the crosstalk is the amount of signal that leaks into the test channel and is expressed in db. reference voltage temperature coefficient reference voltage temperature coefficient is derived from the typical shift of output voltage at 25c on a sample of parts at the maximum and minimum reference output voltage (v ref ) meas- ured at t min , t(25c), and t max . it is expressed in ppm/c as 6 10 ) C ( ) c 25 ( ) ( C ) ( ) c ppm/ ( = min max ref ref ref ref t t v min v max v tcv where: v ref ( max ) = maximum v ref at t min , t(25c), or t max . v ref ( min ) = minimum v ref at t min , t(25c), or t max . v ref (25 c ) = v ref at 25c. t max = +85c. t min = C40c.
preliminary technical data AD7689 rev. prc | page 11 of 20 theory of operation sw+ msb 16,384c in+ lsb comp control logic switches control busy output code cnv cap gnd in- or com 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c -005 figure 11. adc simplified schematic overview the AD7689 is an 8-channel, 16-bit, charge redistribution successive approximation register (sar), analog-to-digital converter (adc). the AD7689 is capable of converting 250,000 samples per second (250 ksps) and powers down between conversions. for example, when operating with an external reference at 1 ksps, it consumes tbd w typically, ideal for battery-powered applications. the AD7689 contains all of the components for use in a multi- channel, low power, data acquisition system including: ? 16-bit sar adc with no missing codes ? 8-channel, low crosstalk multiplexer ? internal low drift reference and buffer ? temp er ature s ens or ? selectable 1-pole filter ? channel sequencer all of which are configured through a spi compatible, 14-bit register. the AD7689 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency. the AD7689 uses a simple spi interface for configuring and receiving conversion results. the AD7689 is specified from 2.3 v to 5.5 v and can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 20-lead, 4mm x 4mm lfcsp that combines space savings and allows flexible configurations. it is pin-for-pin compatible with the 16-bit ad7682, ad7699 and 14-bit ad7949. converter operation the AD7689 is a successive approximation adc based on a charge redistribution dac. figure 11 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? (or com) inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in+ and in- (or com) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and cap, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /32,768). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the AD7689 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
AD7689 preliminary technical data rev. prc | page 12 of 20 transfer functions with the inputs configured for unipolar range (single ended, com with ground sense, or paired differentially with in- as ground sense), the data output is straight binary. with the inputs configured for bipolar range (com = v ref /2, or paired differentially with in- = v ref /2), the data outputs are twos complement. the ideal transfer characteristic for the AD7689 is shown in figure 12 and table 8 for both unipolar and bipolar ranges with the internal 4.096v reference. 100...000 100...001 100...010 011...101 011...110 011...111 2?s comp straight binary 000...000 000...001 000...010 111...101 111...110 111...111 adc code analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb -015 figure 12. adc ideal transfer function table 8. output codes and ideal input voltages description unipolar analog input 1 v ref = 4.096 v digital output code (straight binary hex) bipolar analog input 2 v ref = 4.096 v digital output code (2s complement hex) fsr ? 1 lsb 4.095938 v 0xffff 3 +2.047938 v 0x7fff midscale + 1 lsb 2.048063 v 0x8001 62.5 v 0x0001 midscale 2.048 v 0x8000 0 0x0000 4 midscale ? 1 lsb 2.047938 v 0x7fff -62.5 v 0xffff 3 ?fsr + 1 lsb 62.5 v 0x0001 -2.047938 v 0x8001 ?fsr 0 v 0x0000 4 -2.048 v 0x8000 1 with com or in- = 0 v or all inx referenced to gnd. 2 with com or in- = v ref /2. 3 this is also the code for an overranged an alog input ((in+) ? (in- ) , or com, above v ref ? v gnd ). 4 this is also the code for an underranged analog input ((in+) ? (in-), or com, below v gnd ). typical connection diagram figure 13 shows an example of the recommended connection diagram for the AD7689 when multiple supplies are available. AD7689 ref gnd vdd vio din sck sdo cnv 3-wire interface 4 100nf 100nf 5v 22f 2 v+ v? 1.8v to vdd 0to v ref v+ v? ada4841-x 3 ada4841-x 3 1 internal refernce shown. see reference section for reference selection. 2 c ref is usually a 22f ceramic capacitor (x5r). 3 see driver amplifier section for additional recommended amplifiers. 4 see the digital interface section for configuring and reading conversion data. -006 in0 inn com refin 100nf 0to v ref 0 v or v /2 ref figure 13. typical application diagram with multiple supplies
preliminary technical data AD7689 rev. prc | page 13 of 20 configuration register, cfg the AD7689 uses a 14-bit configuration register (cfg[13:0]) for configuring the inputs, channel to be converted, 1-pole filter bandwidth, reference, and channel sequencer. the cfg is latched msb first with din synchronized to sck rising edge. at the end of conversion, the register is updated allowing the new settings to be used. there is always a one deep conversion delay regardless of when the cfg is written to; during or after conversion. note that at power up, the cfg is undefined and a dummy conversion is required to update the register. to preload the cfg with a factory setting, hold din high for 1 conversion. thus cfg[13:0] = 0x3fff. this sets the AD7689 for: ? in[7:0] unipolar referenced to gnd, sequenced in order ? full bandwidth for 1-pole filter ? internal reference/temp sensor disabled, buffer enabled ? no read back of cfg table 9 summarizes the configuration register bit details. each corresponding section, where necessary, highlights further details of the bits used for the specific functions. table 9. configuration register description bit name description 13 cfg 0 C keep current config settings 1 C overwrite contents of register 12:10 incc input channel configuration 12 11 10 function 0 0 x bipolar differential pairs, in- referenced to v ref /2 0 1 0 bipolar, in0-in7 referenced to com = v ref /2 0 1 1 temperature sensor 1 0 x unipolar differential pairs, in- referenced to gnd (100mv) 1 1 0 unipolar, in0-in7 referenced to com = gnd (100mv) 1 1 1 unipolar, in0-in7 referenced to gnd (single ended) 9:7 inn channel selection in binary fashion 9 8 7 function 0 0 0 in0 0 0 1 in1 . . . 1 1 1 in7 6 bw selects bw for low pass filter 0 C ? of bw 1 C full bw 5:3 ref reference/buffer selection 5 4 3 function 0 0 0 internal ref, ref = 2.5v output 0 0 1 internal ref, ref = 4.096v output 0 1 0 external ref, temp enabled 0 1 1 external ref, internal buffer, temp enabled 1 1 0 external ref, temp disabled 1 1 1 external ref, internal buf, temp disabled 2:1 seq channel sequencer 2 1 function 0 0 disable sequencer 0 1 update config during sequence 1 0 scan in0Cinn (set in cfg[9:7]) then temp 1 1 scan in0Cinn (set in cfg[9:7]) 0 rb read back 0 C read back current configuration at end of data 1- do not read back contents of configuration analog inputs input configurations figure 14 shows the different methods for configuring the analog inputs with cfg[12:10]. gnd -007 com ch0+ ch3+ ch1+ ch2+ ch4+ ch5+ ch6+ ch7+ ch0+ ch3+ ch1+ ch2+ ch4+ ch5+ ch6+ ch7+ com- gnd com in1 in0 in2 in3 in4 in5 in6 in7 in1 in0 in2 in3 in4 in5 in6 in7 in1 in0 in2 in3 in4 in5 in6 in7 in1 in0 in2 in3 in4 in5 in6 in7 a- 8 channels, single ended b - 8 channels, common refernce gnd com ch0+ (-) ch1+ (-) ch2+ (-) ch3+ (-) ch0- (+) ch1- (+) ch0+ (-) ch1+ (-) ch0- (+) ch1- (+) ch2- (+) ch3- (+) c - 4 channels, differential gnd com ch2+ ch3+ ch4+ ch5+ d - combination com- { { { { { { figure 14. multiplexed analog input configuraitons the analog inputs can be configured as: ? figure 14a, single ended referenced to system ground; cfg[12:10] = 111 2 . ? figure 14b, bipolar differential with a common reference point, com, = v ref /2; cfg[12:10] = 010 2 . unipolar differential with com connected to a ground sense; cfg[12:10] = 110 2 . ? figure 14c, bipolar differential pairs with inx- referenced to v ref /2; cfg[12:10] = 00x 2 . unipolar differential pairs with inx- referenced to a
AD7689 preliminary technical data rev. prc | page 14 of 20 ground sense; cfg[12:10] = 10x 2 . in this configuration, the in+ is identified by the channel in cfg[9:7]. example: for in0 = in1+ and in1 = in1-, cfg[9:7] = 000 2 ; for in1 = in1+ and in0 = in1-, cfg[9:7] = 001 2 ? figure 14d, sows the inputs configured in any of the above combinations as the AD7689 can be configured dynamically. sequencer the AD7689 includes a channel sequencer useful for scanning channels in a in0 to inn fashion. channels are scanned as single or pairs and with or without the temperature sensor, after the last channel is sequenced. the sequencer starts with in0 and finishes with inn set in cfg[9:7]. for paired channels, the channels are paired depending on the last channel set in cfg[9:7]. note that the channel pairs are always paired in(even) = inx+ and in(odd) = inx- regardless of cfg[7]. to enable the sequencer, cfg[2:1] are written to for initializing the sequencer. after cfg[13:0] is updated, din must be held low while reading data out (at least for bit 13) or the cfg will begin updating again. while operating in a sequence, the cfg can be changed by writing 01 2 to cfg[2:1]. however, if changing cfg[11] (paired or single channel) or cfg[9:7] (last channel in sequence), the sequence will reinitialize and convert in0 (or in1) after cfg is updated. examples (only bits for input and sequencer are highlighted) scan all in[7:0] referenced to com = gnd sense with temperature sensor: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg incc inn bw ref seq rb - 1 1 0 1 1 1 - - - - 1 0 - scan 3 paired channels without temperature sensor and referenced to v ref /2: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg incc inn bw ref seq rb - 0 0 x 1 0 x - - - - 1 1 - scan 4 paired channels referenced to a gnd sense with temperature sensor: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg incc inn bw ref seq rb - 1 0 x 1 1 x - - - - 1 0 - input structure figure 15 shows an equivalent circuit of the input structure of the AD7689. the two diodes, d1 and d2, provide esd protection for the analog inputs, in[7:0] and com. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this causes the diodes to become forward biased and to start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers supplies are different from vdd. in such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part. c in r in d1 d2 c pin in+ or in- or com gnd v dd -009 figure 15. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in n + and com or in n + and in n -. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 3.5k and is a lumped component made up of serial resistors and the on resistance of the switches. c in is typically 27 pf and is mainly the adc sampling capacitor. selectable low pass filter during the conversion phase, where the switches are opened, the input impedance is limited to c pin . while the AD7689 is acquiring, r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. the low pass filter can be programmed for the full bandwidth or ? of the bandwidth with cfg[6] as shown in table 9. driver amplifier choice although the AD7689 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the AD7689. note that the AD7689 has a noise much lower than most of the other 16-bit adcs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. the noise coming from the amplifier is filtered by the AD7689 analog input circuit low- pass filter made by r in and c in or by an external filter, if one is used. because the typical noise of the AD7689 is 35 v rms (with v ref = 5v), the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3db 2 ) ( f 2 35 35 20log n loss ne snr
preliminary technical data AD7689 rev. prc | page 15 of 20 where: f C3db is the input bandwidth in mhz of the AD7689 (1.7mhz in full bw or 425khz in ? bw) or the cutoff frequency of an input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the AD7689. tbd shows the AD7689s thd vs. frequency. ? for multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7689 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. table 10. recommended driver amplifiers amplifier typical application ada4841-x very low noise, small, and low power ad8655 5 v single supply, low noise ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single supply, low power when the source impedance of the driving circuit is low, the AD7689 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. voltage reference output/input the AD7689 allows the choice of either a very low temperature drift internal voltage reference, an external reference or an external buffered reference. the internal reference of the AD7689 provides excellent perfor- mance and can be used in almost all applications. there are a possible 6 choices of voltage reference schemes briefly described in table 9 with further details in each of the following sections. internal reference/temperature sensor the internal reference can be set for either 2.5v or a 4.096v output as detailed in table 9. with the internal reference enabled, the band-gap voltage will also be present on the refin pin, which requires an external 0.1 f capacitor. enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7689 thus useful for performing a system calibration. note that when using the temperature sensor, the output is straight binary referenced from the AD7689 gnd pin. the internal reference is temperature-compensated to within 15 mv. the reference is trimmed to provide a typical drift of 3 ppm/c. this typical drift characteristic is shown in tbd. external reference and internal buffer for improved drift performance, and external reference can be used with the internal buffer. the external reference is con- nected to refin and the output is produced on the ref pin. there are two modes which can use en external reference with the internal buffer; one with the temperature sensor enabled and one without. refer to table 9 for the register details. with the buffer enabled, the gain us unity and limited to input/output of 4.096v. the internal reference buffer is useful in multi-converter applications since a buffer is typically required in these applications. also, the use of a low power reference can be used since the internal buffer provides the necessary performance to drive the sar architecture of the AD7689. external reference in any of the six modes, an external reference can be connected directly on the ref pin since the output impedance of ref is > 5k ohms. to reduce power consumption, the reference and buffer can be powered down independently or together for the lowest power consumption. however, for applications requiring the use of the temperature sensor, the reference needs to be active. refer to table 9 for register details. for improved drift performance, an external reference such as the adr43x or adr44x is recommended. reference decoupling whether using an internal or external reference, the AD7689 voltage reference output/input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr capacitor connected to ref and gnd with minimum parasitic inductance. a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate when using either the internal reference, the adr43x / adr44x external reference or from a low impedance buffer such as the ad8031 or the ad8605 . the placement of the reference decoupling is also important to the performance of the AD7689, as explained in the layout section. the decoupling capacitor should be mounted on the same side as the adc right at the ref pin with a thick pcb trace. the gnd should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl.
AD7689 preliminary technical data rev. prc | page 16 of 20 regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. for applications that use multiple AD7689s or other pulsar devices, it is more effective to use the internal reference buffer to buffer the external reference voltage thus reducing sar conversion crosstalk. the voltage reference temperature coefficient (tc) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the tc. for instance, a 15 ppm/c tc of the reference changes full-scale by 1 lsb/c. power supply the AD7689 uses three power supply pins: two core supplies, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd pins can be tied together. the AD7689 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range. the AD7689 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. this makes the part ideal for low sampling rates (even of a few hertz) and low battery- powered applications. supplying the adc from the reference for simplified applications, the AD7689, with its low operating current, can be supplied directly using the reference circuit shown in figure 16. the reference line can be driven by ? the system power supply directly ? a reference voltage with enough current output capability, such as the adr43x/adr44x ? a reference buffer, such as the ad8031 , which can also filter the system power supply, as shown in figure 16 ad8031 AD7689 vio cap vdd 22f 1f 10 ? 10k ? 5v 5v 5v 1f 1 1 optional reference buffer and filter. -010 figure 16. example of an application circuit digital interface the AD7689, uses a simple 4-wire interface and is compatible with spi, qspi, digital hosts, and dsps, for example, blackfin? adsp-bf53x or adsp-219x. the interface uses the cnv, din, sck, and sdo signals and allows cnv, which initiates the conversions, to be independent of the read back timing. this is useful in low jitter sampling or simultaneous sampling applications. cfg writing prior to conversion, the AD7689 needs the cfg written to unless the factory default setting is to be used as described in the beginning of the configuration register section. if din is high during the 1 st sck falling edge, cfg will be updated on the 14 th falling sck edge. after the 14 th sck, the cfg will be disabled and not accept any new cfg data until after the end of conversion, t conv (max). the cfg must be updated before the end of conversion for the setting to take effect for the next conversion. it can also be updated while reading back data thus minimizing the sck activity. conversion data the conversion data can be read at any time; during acquisition, during conversion and after conversion. while reading during conversion, the data read is from the previous conversion ( n-1 ) as the current conversion ( n ) is active. the AD7689 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled when the cnv is held low before the maximum conversion time, t conv (max). note that in the following sections, the timing diagrams indicate digital activity (sck, cnv, din) during the conversion. however, due to the possibility of performance degradation, digital activity should only occur prior to the minimum conversion time, t conv (min) since the AD7689 provides error correction circuitry that can correct for an incorrect bit during this time. the user should configure the AD7689 and initiate the busy indicator (if desired) during this time. it is also possible to corrupt the sample by having sck or din transitions near the sampling instant. therefore, it is recommended to keep the digital pins quiet for approximately 30 ns before and 10 ns after the rising edge of cnv. to this extent, it is recommended, to use a discontinuous sck whenever possible to avoid any potential performance degradation.
preliminary technical data AD7689 rev. prc | page 17 of 20 without busy indicator this mode is usually used when the AD7689 is connected to an spi-compatible digital host. the connection diagram is shown in figure 17, and the corresponding timing is given in figure 18. a rising edge on cnv initiates a conversion and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this could be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. configuring the AD7689 for the (n + 1) conversion is initiated when sck is high and a rising edge on cnv. after this mode is initiated, cnv is a dont care as the cfg word is written in msb first with 14 sck rising edges. as shown in figure 18, cfg is written to during the current ( n ) conversion before the end of conversion, or t conv minimum time. at the end of conversion, the register is updated. in this mode, the new configuration settings are used for the following (n + 1) acquisition and conversion. the AD7689 can also be configured on 14 scks of the data reading (not shown), thus reducing the number of sck bursts. however, this new cfg setting is for the (n + 2) conversion since the ( n ) conversion has ended. this mode is useful when using multiple AD7689s using the same configuration. when the conversion is complete, the AD7689 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. data in cfg data clk convert cnv sck sdo din AD7689 digital host - 01 1 figure 17. without busy indicator connection diagram d15 d14 d13 d2 d1 t dis sck 1 23 1 23 13 14 t sck t sckl t sckh t hsdo t dsdo t sdin t hdin t csck conversion (n) conversion (n + 1) acquisition (n) acquisition (n + 1) t conv t cyc t cnvh t acq t en -012 cnv 14 15 16 d0 din sdo c13 c12 c11 c1 c0 figure 18. without busy indi cator serial interface timing
AD7689 preliminary technical data rev. prc | page 18 of 20 with busy indicator this mode is usually used when the AD7689 is connected to an spi-compatible digital host using an interrupt input. the connection diagram is shown in figure 19,, and the corresponding timing is given in figure 20. a rising edge on cnv initiates a conversion and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. configuring the AD7689 for the (n + 1) conversion is initiated when sck is high and a rising edge on cnv. after this mode is initiated, cnv is a dont care as the cfg word is written in msb first with 14 sck rising edges. as shown in figure 20, cfg is written to during the current ( n ) conversion before the end of conversion, or t conv minimum time. at the end of conversion, the register is updated. in this mode, the new configuration settings are used for the following (n + 1) acquisition and conversion. note that sck must be high when cnv goes high for this configuration mode. the AD7689 can also be configured on the first 14 sck of the data reading (not shown), thus reducing the number of sck bursts. however, this new cfg setting is for the (n + 2) conversion. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by th e digital host. the AD7689 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple AD7689s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. data in cfg data clk convert cnv sck sdo din AD7689 digital host - 013 vio irq figure 19. with busy indicator connection diagram d15 d14 d13 d3 d2 t dis sck 1 23 1 23 13 14 t sck t sckl t sckh t hsdo t dsdo t sdin t hdin t csck conversion (n) conversion (n + 1) acquisition (n) acquisition (n + 1) t (max) conv t (min) conv t cyc t acq -014 cnv 14 15 16 d1 d0 din sdo c13 c12 c11 c1 c0 17 4 figure 20. wwith busy indicator serial interface timing
preliminary technical data AD7689 rev. prc | page 19 of 20 application hints layout the printed circuit board that houses the AD7689 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD7689, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7689 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the AD7689s. the AD7689 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the power supplies vdd and vio of the AD7689 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the AD7689 and connected using short, wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 21 and figure 22. evaluating AD7689 performance other recommended layouts for the AD7689 are outlined in the documentation of the evaluation board for the AD7689 ( eval-AD7689cbz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3z . figure 21. example layout of the AD7689 (top layer) figure 22. example layout of the AD7689 (bottom layer)
AD7689 preliminary technical data rev. prc | page 20 of 20 outline dimensions 2.65 2.50 sq 2.35 3.75 bcs sq 4.00 bsc sq compliant to jedec standards mo-220-vggd-1 081407-b 1 0.50 bsc p i n 1 i n d i c a t o r 0.50 0.40 0.30 top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 20 6 16 10 11 15 5 exp o se d pad (bott om view) 0.60 m a x 0.60 max 0.25 min figure 23. 20-lead lead frame chip scale package (lfcsp_vq) 4 mm 4 mm body, very thin quad (cp-20-4) dimensions shown in millimeters ordering guide ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr07083-0-9/07(prc)

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